Optimal Assignment of High Threshold Voltage for Synthesizing Dual Threshold CMOS Circuits

Development of the process technology for dual threshold (dual Vth ) CMOS circuit has opened up the possibility of using it to reduce static power in low voltage high performance circuits. It has been demonstrated that by using transistors of a low threshold voltage for gates on the critical path, and by using a high threshold voltage for gates in the off-critical path it is possible to significantly reduce leakage power consumption of a circuit without performance degradation. In this paper we have proposed a new algorithm to realize dual threshold CMOS circuits. Our algorithm produces significantly better results for the ISCAS benchmark circuits compared to the reported results. 1.0 Introduction As dynamic power depends quadratically on the supply voltage Vdd and static power is directly proportional to it, supply voltage reduction has the most profound effect on power consumption of CMOS circuits. However, reduction in Vdd leads to an increase in delay, which results in performance degradation of the circuit. Scaling down the threshold voltage Vth by the same factor as Vdd is considered to be a solution to keep the same performance level. Unfortunately, reducing Vth in smaller geometry MOSFETs results in an exponential increase in the static power. Main component of the static power is the subthreshold leakage current. It has been reported that the power dissipation due to this component dominates the dynamic power at low threshold voltages [1]. In portable battery-driven systems, where large portion of circuits remain in standby mode for a long duration, this static power turns out to be a major issue. To alleviate this problem, the use of multiple threshold voltage CMOS (MTCMOS) circuits has been proposed as a viable solution. Technology for dual-Vth CMOS process has been developed making implementation of dual threshold CMOS circuits a reality [8]. Two basic strategies have been proposed for the reduction of standby power using this dual Vth technology. In one, a high-threshold sleep transistor is inserted in series with low-threshold transistor stacks. The sleep transistor is turned off in the standby mode, leading to reduction in standby current. As this strategy suffers from several limitations [8], it is not a preferred approach. The other strategy uses low-threshold transistors for gates on the critical path and high threshold transistors on the offcritical path [2], [9]. In [2], a heuristic-based algorithm was presented which, for a given circuit with a fixed supply voltage (1V) and a fixed low threshold voltage L th V (0.2V) for gates on the critical path, finds a “static power optimum” high threshold voltage H th V , and a subset of the gates in the off-critical path which can be switched to H th V . This approach demonstrated significant savings in leakage power for the optimized circuits without degradation in performance. However, the algorithm in [2] employed simple backward breadth-first search (BFS) strategy to identify the subset of gates that can be switched to H th V . So far as the computational effort is concerned, the said algorithm is fast but it has two inherent drawbacks: i) It selects fewer gates for assigning H th V in the off-critical path; in fact more gates can be assigned leading to more savings in the leakage power. ii) After the assignment of H th V to a gate, the critical path may change. This dynamic change in critical path has not been taken into consideration. Same problem has been addressed in [9], where a “near-optimal approach” has been proposed to obtain further improvements in power saving, in the range of 0% to 29.45%, compared to [2]. In this paper, we have also addressed the same problem and proposed a new algorithm to overcome the limitations mentioned above. As anticipated, we have obtained significant improvement in results over [2] and [9] for the ISCAS benchmark circuits. In Sec. 2 we provide the preliminaries covering the notations used in the subsequent sections. The models for measuring delay and standby leakage power is also presented in this section. In Sec. 3 details of the algorithm is presented. Implementation of the algorithm is described in Sec. 4. Experimental results are furnished in Sec. 5. 2.0 Preliminaries A combinational circuit is represented by a directed acyclic graph G(V, E). Each node (except the primary inputs and primary outputs) in G corresponds to a logic gate in the circuit and each edge maps to a connection in the circuit. The general form of the dual Vth optimization problem is to assign one of the two threshold voltages L th V and H th V to all the transistors of each gate such that some cost function is optimized subject to some constraints. The assigned threshold voltages to different gates are represented by labeling each node v∈V (to which the transistors belong) by a variable xi where xi = 0 (xi =1) means the transistors in vi are with Vth = H th V (Vth = L th V ). The dual selection problem can be viewed in one of the two ways: either delay can be optimized subject to constraints on power or vice versa. Our problem is to reduce the standby leakage power subject to the constraint of not increasing the delay. In order to solve this problem, we need a model to estimate delay and standby leakage power. We have used the same models as used in [2]. These two models are summarized in the following two subsections. 2.1 Delay Estimation The propagation delay through a node x, denoted as tp(x), defines how quickly the outputs responds to a change in the input. The propagation delay of a path Π, denoted as pd(Π), is the sum of the propagation delays tp(i) of each node i along this path Π. It can be expressed as pd(Π) = ∑ ∏ ∀ in i ) (i t p (1) The arrival time Ta(x) is the propagation delay of each fan-in path of node x. among all the fan-in paths, there exists a path (or paths) which has a maximum propagation delay value Tmax(x), where { } fanin all i ] )[ ( max ) ( max ∈ = i x T x T a (2) The departure time Tl(x) of node x is defined as ) ( t ) ( T ) ( p max(x) x x x Tl + = (3) The path, which determines the maximum speed of the circuit, is called the critical path. It can be noted that, there may be more than one critical path. Critical delay (Tcritical) is the delay along the critical path. In [3], a model has been developed for estimating the delay of CMOS VLSI gates based on the commonly used Elmore delay model [7]. According to this model, the worst case propagation delay of a CMOS gate is given by ( ) 2 t t t PLH PHL p + = (4)